Memory cells in memories or logic arrays typically use FET transistors with a floating gate structure. The bit state of a cell depends upon the charge on the insulated floating gate, with the voltage needed to charge the floating gate depending upon the coupling coeficient between a program gate and the underlying floating gate.
The specific problem to which the invention can be applied is the fabrication of an EPROM using an array of vertical floating gate transistor memory cells. A vertical floating gate transistor is described in the related patent--the vertical floating gate structure permits transistors, such as used in memory cells, to be fabricated with less cell area than achievable with current planar technology.
EPROM memories commonly use floating-gate, avalanche-injection, metal-oxide-semiconductor (FAMOS) transistors. To program the EPROM, which are typically N-channel devices, a positive program voltage of a sufficient magnitude is applied to the program gate to cause channel hot electrons to be transferred from the channel region to the floating gate. This program charge may be erased using UV light or other radiation.
To achieve greater bit densities for EPROM chips, memory cell area has been gradually reduced. Conventionally, the floating gate FET transistors used for memory cells have been fabricated in a planar structure, i.e., with a planar source/channel/drain structure at the substrate surface, including a planar floating gate. For a given memory cell size, the chip area assigned to the cell can be minimized by making the array contactless, albeit at the expense of access time--electrical contacts to the program (or control) gate and drain regions for each FET cell are made only at the ends of respective surface wordline columns (forming the program gates) and buried bitline rows (forming the drain regions), thereby avoiding the need for individual contacts (with associated contact areas) to each memory cell.
For planar FET structures in contactless arrays, cell size is largely dependent upon channel length. Channel length is determined by the width of the lines of photoresistive material used as an implant mask for implanting source and drain regions on either side of a photoresist line. Thus, reducing channel length to obtain smaller cell area necessitates improving photoresist masking procedures.
Using current planar fabrication technology, planar EPROM arrays with channel lengths of about one micron are conventional, and channel lengths down to about 0.6 microns are becoming available (albeit at a significantly higher level of capital investment in sub-micron patterning equipment). In addition to reducing cell size, reducing channel length increases channel current for a given read voltage, thereby decreasing access time.
The vertical floating gate structure described in the related patent offers a fabrication technology that allows memory cell area to be significantly reduced from that obtainable with current planar fabrication technology. In addition, channel lengths can readily be reduced to below 0.5 microns, with an attendant decrease in access time.
As described in the related patent, the vertical gate structure is fabricated into a trench surrounded by buried, vertically-stacked source and drain regions separated by a channel region with a predetermined channel length (in the vertical dimension). See Section 1 of the Detailed Description and FIG. 1a.
Accordingly, a need exists for an array structure using vertical floating gate transistor cells, such as for an EPROM, and a method of fabricating such an array.